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March 14-16,2018
Shanghai New International Expo Centre

Symposium II: Lithography and Patterning


(** to designate keynote talk, * to designate invite talk)

Sunday, March 12, 2017, Shanghai International Convention Center

Joint Session: Symposium II and Symposium III-Lithography/Etch joint session
Meeting Room:3rd Floor Yellow River Hall 黄河厅
Session Chairs: Kafai Lai/Ying Zhang


13:30-13:35 Opening Remarks
  Kafai Lai, IBM
**13:35-14:05

The Path Forward: The Future of Optical Lithography

  Donis Flagello, Nikon Research America
**14:05-14:35 Patterning Technology Inflections for the 10nm and Beyond Logic Nodes
  Rich Wise, Lam Research
*14:35-14:55 Considerations for pattern fidelity control towards 5nm node
  Hidetami Yaegashi, TEL
*14:55-15:15

Key points in 14 nm Photolithographic Process Development, Challenges and Process Window Capability

  Qiang Wu, SMIC
15:15-15:30 Coffee Break

Session II: Computational Lithography
Meeting Room: 3rd Floor Yellow River Hall 黄河厅
Session Chairs: Yayi Wei / Shiyuan Liu


**15:30-16:00 Computational Lithography for Process Window Enhancement and Control
  Yu Cao, ASML-Brion
*16:00-16:20 Impact of multi beam on Mask Process Modeling
  Ryan Pearman,D2S
16:20-16:35

The Insertion of extreme ultraviolet lithography (EUVL) from patterning perspective

  Weimin Gao, Synopsys
16:35-16:50 An off-line roughness evaluation software and its application in quantitative calculation of wiggling based on low frequency power spectrum density method
  Zhang Libin, IMECAS
16:50-17:05 Level-set based ILT with Vector Imaging Model Emphasis
  Yijiang Shen, Guangdong University of Technology
   
Poster Session: Location: Foyer of Yangtze River Hall
Coffee Break DOF enhancement of 3bar PO pattern in 28nm Technology Node
  Bin-Jie Jiang, Shanghai Huali Microelectronics Corporation
  Estimated the potential hot spots and provided OPC improved solution based on the light intensity distribution
  Wang Dan, HLMC
  The incorporation of the pattern matching approach into a post-OPC repair flow
  Yaojun DU, SMIC
  The OPC Methods to Improve the Coverage Area of Metal Layers on Via Layer
  Chen Yanpeng, Shanghai Huali Microelectronics Corporation
  Synthesis and Directed Self-assembly of Modified PS-b-PMMA for Sub-10 nm Nanolithography
  Xuemiao Li, Fudan University
  Research of SMO process to improve the lithography system imaging capability for 28nm node and beyond
  Haibin Yu, Shanghai Huali Microelectronics Corporation
  The phenomena of footing’s variation caused by oxidation of nitrogen-containing substrates
  Song Bai, Technology R&D, SMIC Advanced Technology R&D (Shanghai) Corporation
  28nm MPW“Blading Mask”Project Study and Implement
  Shijian Zhang, SMIC
  A Study of N-induced Residue Defect on Gate Oxide after Lithography Rework
  Zhou Fang, Semiconductor Manufacturing International Corp
  Application of Litho-Friendly Design in 28nm Metal Layer
  Wu weiwei, Shanghai Huali Microelectronics Corporation
  Wafer Edge Treatment In Lithography Process For BEOL Peeling Defect Reduction
  Xiaofeng Yuan, Roger_Yuan
  Ultrapure Chemical Components for Next Generation Materials
  Hyunyong Cho, Heraeus
  How to Increase Photoresist lifetime at the extreme condition
  Qiaoqiao Li, Sarah Li
  Illumination Optimization for Lithography Tools OPE Matching at 28 nm Nodes
  Wuping Wang, Shanghai Huali Microelectronics Corporation
  Critical Dimension (CD) variation control of the implant layer with nitride film
  Xiaoyan Sun, SMIC
  Hole Pattern Circularity Improvement with Functional Rinse
  Lei Ye, SMIC
  Diffraction-based and Image-based Overlay Evaluation
  Jian Xu, Shanghai Huali Microelectronics Corporation
  Blob Defect Solution for 28 nm hole pattern in 193 nm topcoat-free immersion lithography
  Dan Li, Shanghai Huali Microelectronics Corporation
  The Optimization of development processes in TC-less immersion process
  Wei-Ming He, SMIC
  A kind of one-component chemically amplified positive photoresist for deep UV lithography
  liyuan wang, College of Chemistry, Beijing Normal University


Monday, March 13, 2017 Shanghai International Convention Center

Joint Session: Symposium II and Symposium IX-DTCO Joint session
Meeting Room: 3rd Floor Yellow River Hall 黄河厅
Session Chairs: Yiyu Shi / Leo Pang


8:30-8:35 Opening Remarks
  Yiyu Shi
**8:35-9:05 Design Technology Co-optimization for Disruptive Patterning Schemes
  Puneet Gupta, UCLA
**9:05-9:35 Software Defined Chip: Technologies, Challenges and Opportunities
  Shaojun Wei, Tsinghua University
*9:35-9:55 Data Analytics and Machine Learning for Design-Process-Yield Optimization in Electronic Design Automation and IC Semiconductor Manufacturing
  Luigi Capodieci, Motovi.ai
9:55-10:10 Coffee Break


Session IV: Tool, Mask & Metrology
Meeting Room: 3rd Floor Yellow River Hall 黄河厅
Session Chairs: Motokatsu Imai/Qiang Wu


*10:10-10:30 Electron beam lithographic modeling assisted by artificial intelligence technology
  Noriaki Nakayamada, NuFlare
*10:30-10:50 Enhancing Light Source Capabilities for the sub-7nm Node
  Will Conley, ASML-Cymer
*10:50-11:10 High accuracy EPE measurement and Litho. Simulation capability for ILT
  Mark Sheppard, Advantest
*11:10-11:30 Advanced CD-SEM metrology for Edge Placement Error (EPE) control in the post Moore Era.
  Takeshi Kato, Hitachi High Technologies
*11:30-11:50 Development of 250W EUV light source for HVM lithography
  Taku Yamazaki, Gigaphoton
11:50-13:20 Lunch Break


Session V: Multiple patterning
Meeting Room: 3rd Floor Yellow River Hall 黄河厅
Session chairs: Wanh Yueh / Zhimin Zhu


13:20-13:35 The solutions for 3D-NAND process with Canon’s latest KrF scanner
  Masanori YAMADA, Canon
13:35-13:50 Enhanced control of overlay and CDU for immersion scanners targeting 7 nm node patterning
  Reiji Kanaya, NIKON
13:50-14:05 The Impact of Double Patterning Decomposition Algorithm on 14nm Metal Layer Patterning
  Qing Yang, SMIC
14:05-14:20 Application of OPE Master for Critical Layer OPE Matching
  Yuan Tao, Nikon Shanghai
14:20-14:35 Coffee Break


Session VI: Process & Material
Meeting Room: 3rd Floor Yellow River Hall 黄河厅
Session chairs: Gyomei Shiba / Hai Deng


**14:35-15:05 Material Challenges for Sub 10nm Lithographic Patterning
  James Cameron, Dow
*15:05-15:25 DDR Process and Materials for NTD Photo Resist
  Shuhei Shigaki, Nissan Chemicals
*15:25-15:45

Advanced Lithographic Filtration and Contamination Control for 14nm node and beyond Semiconductor Processes

  Rao Varannasi, Pall Corporation
15:45-16:00 Novel EUV Resist Development for Sub-14 nm Half Pitch
  Koichi FUJIWARA, JSR Shanghai
16:00-16:15 Advancement in Resist Materials for Sub-7 nm Patterning and Beyond
  Li Li, Global Foundries
*16:15-16:35 Molecular Force Modeling of Lithography
  Zhimin Zhu, Brewster Science
16:35-16:50 Design and synthesis of novel directed self-assembly block copolymers for sub-10 nm lithography application
  Jie Li, Fudan university