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June 27-29, 2020
Shanghai New International Expo Centre

Symposium II: Lithography and Patterning


** to designate keynote talk - 30 min
* to designate invite talk - 20 min
  to designate regular talk - 15 min

Parallel Symposium Oral Sessions: June 29-July 17, 2020

Session I: Lithograpy/Etch joint session (II & III)
** Advanced Memory Patterning Challenges and Perspective Solutions

Jeongdong Choe, DRAM
** The Law that Guides the Development of Photolithography Technology and the Methodology in the Design of Photolithographic Process
  Qiang Wu, Shanghai IC R&D Center
Session II: Computational Lithography
* High-NA EUV lithography enabling cost-effective shrink patterning

Jara G. Santaclara, ASML
* Accurate etch modeling with high-volume metrology and deep-learning technology

Wei Yuan, ICRD

AI Computational Lithography

Xuelong Shi, ICRD

Accurate mask model approaches for wafer hot spot prediction and verification

Young Mog Ham, Photronics

Etch Proximity Correction Based on Machine Learning

Rui Chen, IMECAS

Simulation Study for Typical Design Rule Patterns and Stochastic printing failures in 5 nm Logic Process with EUV Photolithographic Process

Yanli Li, ICRD
Parallel Session
* TBD

Thomas Schrubel, Zeiss
* EUV lithography and metrology for more Moore

Yasin Eckinci, Paul Scherer Institute

Mitigation of microbridging defects in EUV lithography through advanced filtration technologies

Toru Umeda, Nihon Pall Ltd.

Second order diffraction EUV interference lithography for the study of highresolution EUV resists

Xiaolong Wang, Paul Scherer Institute

Development of 90 nm & 5 nm patterning materials for lithographic technology

Hai Deng, Fudan University
Session III: DTCO Joint session ( II & IX)
** Monolithic 3D enabled Processing-in- SRAM Memory
  Vijaykrishnan Narayanan, Pennsylvania State University
** TBD

Steffen Schulz, Mentor Graphics
** Full Chip Curvilinear ILT in a Day

Leo Pang, D2S
Session IV: Multiple patterning
* Multi-focal imaging; Principles and application for improving DOF in an Advanced 3D NAND Via Layer

Will Conley, Cymer
* A Study of Image Contrast, Stochastic Defectivity, and Optical Proximity Effect in EUV Photolithographic Process under Typical 5 nm Logic Design Rules

Qiang Wu, ICRD
* DuPont's Embedded Layer Technology that Enables Advanced Lithography

Mingqi Li, Dupont Electronics

The topography effect on the lithography patterning control for VLSI fabrication

Dongyu Xu, Huali

Advanced Patterning technology by evolution on process integration and equipment

Inagaki Naoki, TEL
Session V: Tool, Mask & Metrology
** Challenge of High Power LPP-EUV Source with Long Collector Mirror Lifetime for Semiconductor HVM

Hakaru Mizaguchi, Gigaphoton
* Line Width and Roughness Measurement of Advanced FinFET Features by Reference Metrology

Mamsami Ikota, Hitachi High Tech

High Speed Wafer Geoemtry on Silicon Wafers Using Wave Front Phase Imaging for Inline Metrology

Jan Gaudestad, Wooptix
Session VI: Process & Material
* Advanced Lithography Material Status toward 5nm Node and beyond

Kouichi Fujiwara, JSR

How to improve' Chemical Stochastic' in EUV lithography ?

Toru Fujimori, Fujifilm Corp.
* Novel Spin on Planarization Technology by Photo Curing SOC

Hikaru Tokunaga, Nissan Chemicals
* VASE innovation for ultrathin film characterization

Zhimin Zhu, Brewer Science

Evolution of Underlayer Materials for Enhancement of Lithographic Patterning

Jae Hwan Sim, DuPont Electronics & Imaging Korea Technology Center
* Are Surfaces of Silicon Hardmasks Adaptive?
  Xianggui Ye, Brewer Science

Conference Poster Session: June 26-July 17, 2020

  Impacts of RTP pyrometer offsets on wafer overlay residue

Lv Jian, HLMC  
  Mix and Match Overlay Improvement of 55nm M1 Layer On Nikon Immersion Scanner
  Ma Yuanzhao, Nikon Precision Shanghai
  Study of Positive Tone Photoresist Thin Film Homogeneity at Nanoscale During Lithographic Process Using Massive Cluster Secondary Ion Mass Spectrometry
  Mingqi Li, Dupont Electronics & Imaging
  APPLICATIONS OF SPARSE AND COMPACT RESIST MODELING IN ADVANCED NODE IMPLANT LAYER
  MudanWang, HLMC
  Optical Scatterometry Modeling of 5 nm Structures with RCWA Method and Perfectly Matching Layer (PML) Boundary Conditions
  Aihua Yang, Shanghai IC R&D Center
  EVALUATING THE PROCESS PERFORMANCES OF BINARY, PSM AND OMOG MASKS IN 14NM TECHNOLOGY NODE
  Xie Weimei, Chen Yanpeng, Yu Shirui, HLMC
  Study of alignment & overlay strategy in 14nm lithography process
  Lulu Lai, HLMC
  Litho Process Optimization to Improve Overlay Measurement in Thick PR Layer
  Jiantao Wang, HLMC
  Effects of Electron Beam on Photo Resist Shrinkage and Critical Dimension in SEM Measurement
  Yuyang Bian, HLMC
  Enlarge Process Window of BSI in DTI Loop :A Novel OPC Approach to Add SRAF
  Qiao Yanhui, HLMC
  Solvement of TEOS residues during 19NAND process
  Fang Ma, Shanghai Huali Microelectronics Corporation
  Critical Dimension Uniformity Improvement of Negative Toned Developing Process for Hole Type Pattern
  Rui-Lin Zhang, Semiconductor Manufacturing International Corp
  Mask fidelity improvement using different MPC techniques
  Mohamed Ramadan, Photronics