| ** | to designate keynote talk |
| * | to designate invite talk |
| to designate regular talk |
Session I: Agile Design for Advanced Ics
| *Interesting technical challenges in FPGA-based prototyping and emulation (11:00-11:35, June 17, Microsoft Teams Meeting) |
| Pei-Hsin Ho, Shanghai UniVista Industrial Software Group |
| *Agile Hardware Specialization for Spatial Architecture (14:00-14:30, June 17, Microsoft Teams Meeting) |
| Yun Liang, Peking University |
| *Algorithm and architecture co-optimization for PIM-based DNN accelerators (14:30-15:00, June 17, Microsoft Teams Meeting) |
| Li Jiang, Shanghai Jiaotong University |
| Using Mixed Logic Synthesis Tools in Open-Source FPGA Design Framework |
| Liangtao Shi, Ningbo University |
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Session II: Analog Design Automation
| *Topology Optimization of Analog Circuits via Graph Embedding |
| Fan Yang, Fudan University |
| *Capacitance Extraction: From Random Walk to Machine Learning |
| Wenjian Yu, Tsinghua University |
| *Design-for-Recovery Techniques for Combating Chip Aging Issues |
| Xinfei Guo, University of Michigan – Shanghai Jiao Tong University Joint Institute |
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Session III: Perspective and Frontier of EDA
| **Agile and Intelligent Design Automation for Digital/Analog/Mixed-Signal Ics |
| David Pan, University of Texas at Austin(UT Austin) |
| *Analytical Optimization Method for VLSI Global Placement |
| Weijie Chen, Fudan University |
| *Dynamic stochastic computing and its applications |
| Siting Liu, Shanghai Tech University |
| *Area-aware optimization of XOR-AND Graph based on Reed-Muller logic expansion |
| Hongwei Zhou, Ningbo University |
Session IV: Design Perspective from Industry
| *How to design SSD controller for Enterprise & Datacenter |
| Dawei Wu, YEESTOR Microelectronics Co., Ltd |
| *Research on key technologies of ultra-high speed data transmission in Big Data Era |
| Zhi-Qiang Guan, Suzhou Chiptel Microelectronics Co., Ltd |
| *A Survey of Domain Specific Architecture Innovations in AI Chip Industry |
| Gongyifan Yang, CLTech |
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SESSION V: Design for Energy Efficiency
| **Polynomial Formal Verification of General Tree-like Circuits (13:30-14:00, June 17, Microsoft Teams Meeting) |
| Alireza Mahzoon, University of Bremen |
| *Graph Neural Networks and Reinforcement Learning in EDA |
| Cong Hao, Georgia Institute of Technology |
| *Towards Independent On-Device AI: Inference without Battery and Learning without Labels |
| Jingtong Hu, University of Pittsburgh |
| A FPGA-Based Verification Platform for High-Speed Interface Ips |
| C.-Z. Chen, Zhejiang University |
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Session VI: Low Power Design and Design Methodology
| *Hybrid Memristor/CMOS neuromorphic circuits |
| Peng Lin, Zhejiang University |
| Automatic placement algorithm of integrated circuits for wire bond packaging application |
| Haochen Wang, Fudan University |
| Integrated Superconducting Isolator-Circulator-Isolator Device |
| Rutian Huang, Tsinghua University |
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Poster Session:
| A Gaussian Process and Multi-Swarm optimizer Assisted Optimization Approach for Analog Circuit Design |
| Xu Fu, Fudan University |
| Design based on simplified Doherty power amplifier with harmonic control |
| Hao Zhou, Nanjing University of Posts and Telecommunications |
| An Approximating Twiddle Factor Coefficient Based Multiplier for Fixed-Point FFT |
| Songyu Sun, Zhejiang University |
| Fast Dynamic IR Drop Prediction with Machine Learning |
| Xiao Dong, Zhejiang University |
| A Fast Timing Analysis and Optimization for Latch-based Circuits |
| Kaixiang Zhu, Fudan University |
| A Transient-Improved spike time reduction circuit for LDO |
| ZongYuan Zheng, School of Electronic and Computer Engineering, Peking University Shenzhen Graduate School |
| Rule Check of Pad Placement in IC Layout with Yolo V3 |
| Tao Su, Sun Yat-sen University |
| Study on Optimization Design Method of QCA-Based Circuit |
| Lei Wang, Space Engineering University |
| Bayesian Inference-based Error Computation for Approximate Computing |
| Weihua Xiao, Shanghai Jiao Tong University |