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March 14-16,2018
Shanghai New International Expo Centre

Dr. Frank Feng

Dr. Frank Feng
Mentor Graphics Corporation,America

15+ years of EDA product development, support, marketing, and customer engagement experience. 3 years of foundry diffusion / thin-film process experience. Major job function in initiating, engaging, and managing qualification process for Calibre Physical / Circuit Verification / DFM / ESD-LatchUp / Reliability sign-off design kits with TSMC / UMC / SMIC. Frequently promoting new EDA product & feature and providing pre-sale technical support for customers in North America and Pac Rim. Closely working with foundry and field team to accomplish customer timely goal. Devote to provide reliable design solution to achieve quality silicon for customer, return customer engagement experience to improve product quality, and create new product to enhance company business. Highly self-motivated, has strong project managing, problem solving, engineering, and presentation skill. Excellent team working spirit and strong communication skill to balance customer request and product development roadmap.

PROFESSIONAL EXPERIENCE

Mentor Graphics Corporation, Wilsonville, Oregon
Circuit Verification Methodologist / Product Manager / Technical Marketing Engineer, 2005 - present
· Initiate and co-develop Connectivity Aware Layout Selection methodology for high performance full chip Power / Ground ESD P2P measurement
· Initiate Calibre PERC engagement with Intel QRE; Key player supporting QRE / ICF for development of EOS / ESD kit
· Lead advanced technology tech file & design kit qualification for Calibre PERC for reliability related ESD / Latch-Up / EOS / ERC applications with TSMC / SMIC / UMC. The process includes presenting product / feature capability to initiate the engagement, reviewing customer requirement, optimizing customer requirement, proposing implementation specification for R&D, working out delivery schedule with R&D and customer, following up action items / design kit preparation / testing / debug, complete QA on customer designs, documentation, complete design kit delivery, and training
· Initiate and co-develop LEF / DEF cell based ESD path resistance measurement flow for Calibre PERC with Panasonic
· Successful pre-sale Calibre PERC engagement lead to production adoption for Altera / Apple / MediaTek / NECEL / Fujitsu / HiSilicon / Samsung / Hynix
· Initiate and co-develop schematic driven layout checking platform for Calibre PERC for reliability verification
· Lead advanced technology PDK qualification for Calibre nmLVS with TSMC
· Lead advanced technology PDK qualification for Calibre DFM features -- YieldEnhancer / YieldAnalyzer with TSMC / UMC. YieldEnhancer (double via / edge expansion / smart metal fill) and YieldAnalyzer (Critical Area Analysis / Critical Geometry Feature Analysis) are design methodologies to optimize silicon yield
· Lead and develop Calibre Critical Area Analysis easy-to-use GUI
· Lead and develop high performance algorithm for Calibre Critical Area Analysis for huge particle size
· Coordinate internal foundry team activity and resource
· Optimize product requirement between customer/field team and R&D
· Propose product implementation specification for R&D
· Debug & quality testing for R&D product implementation
· Product presentation & demo in DAC / EDA Tech Design Forum
· Participate technical review meeting with major customers
· Joint press release with customer to announce product adoption
· Internal field AE/ External customer product training / workshop

Synopsys / Avanti, Hillsboro, Oregon
Corporate Application Engineer / Product Specialist, 2001-2005
·Corporate Application Engineer: Primary engagement / support of place & route methodology for Intel 65 nm CPU project. ASIC benchmark engagement on timing / DRC closure and chip size control at final stage of sale deal signing. Develop (Alpha & Beta) product test of Astro place, timing optimization, and routing engine. Very skillful with layout P&R tool (Astro, Physical Compiler, Apollo), Floor Planning tool (JupiterXT), timing sign-off tool (PrimeTime).
·Product Specialist: Remote / on-site primary support of physical layout (floor planning, place & route) methodology (by EDA tool of Jupiter / Apollo / Astro) for Intel 90 nm CPU project (code name Prescott) tape out. Define Spec and construct Demo for design specific floor plan tool. Conduct layout timing & routing Benchmark for Agere / Intel design. Debug / enhance EDA tool (Milkyway / Apollo / Astro / Jupiter). Assist EDA tool marketing & sales.

WaferTech Inc. (TSMC Fab in USA), Camas, Washington
Process Engineer, 1998-2001
·Team Leader: Initiate / manage project for device yield enhancement. Categorize defect for tool performance improvement. Design short loop process flow for debugging device integration failure. Develop tool process log to standardize process parameter control. Maintain Statistic Process Control for all Diffusion tools. Implement diffusion engineering training and process tuning guide. Revise document. ISO 9000 & Customer audit. Set up Microsoft Excel-Visual Basic automation application for tool SPC event log.
·Module Owner: Qualify new equipment (Gate Oxide, Poly, Nitride, TEOS, HTP, DCS-WSix) process. Maintain tool daily process performance (particle, film thickness, film sheet resistance) to meet Cpk goal. Troubleshoot AMAT CENTURA CVD chamber mismatch, KE Furnace zone to zone non-uniformity. Improve device yield-sensitive process control. Improve recipe / identify hardware modification to increase throughput. Revise monitor procedure and chemical usage to reduce cost. Develop automatic multiple process/chamber/zone monitor flow. SEM/EDX for defect or failure analysis.

Texas Center for Superconductivity, Houston, Texas.
Research Scientist, 1996-1998
· Develop epitaxial high dielectric/superconductive multiple layered oxide film by rf Sputtering/Laser Ablation/CVD.
· Integrate induction coil, SQUID sensor, cryogenic system, and electronics into SQUID-Eddy current system for nondestructive 3-D metal failure/fatigue evaluation.
· Hardware and software integration for control and measurement automation.
PUBLICATION & PATENT
· /http://semimd.com/favre/2014/05/05/full-reliability-automation-is-here
· http://semimd.com/favre/2014/10/24/my-designs-interconnect-has-enough-wire-width-to-withstand-esd -doesnt-it/
· http://ieeexplore.ieee.org/xpls/abs_all.jsp?arnumber=7153480
· Patent: Layout Data Reduction For Design Verification -- pending

EDUCATION
· Ph.D., Physics, University of Houston, Houston, Dec. 1995.
· BS, Physics, National Cheng Kung University, Taiwan, 1986.

COMPUTER SKILL / LANGUAGE PROFICIENCY
· Linux / Window OS based application and programming
· English and Mandarin