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+86.21.6027.8500
English
March 14-16,2018
Shanghai New International Expo Centre

3DIC Technology Forum 2013

SEMICON China - 同期研讨会/活动 - 超越摩尔技术论坛

3DIC Technology Forum                           

Date: Wednesday, March 20, 2013  
Time: 08:30 – 16:50
Venue: Ballroom 2&3,Kerry Hotel Pudong, Shanghai
Note: Chinese and English Simultaneous Interpretation will be provided on-site.
 

Sponsored by:   
 

                          

Program Brief

Nowadays, electronic products are becoming shorter, smaller, thinner, and lighter. To meet these requirements, we need to scale down the wafer size according to Moore’s Law. However, as the scale of the chip size shrinks, Moore’s Law has reached its limit. What shall we do beyond Moore’s Law? SEMI China will hold a forum to discuss the solution of 3D Integration and analyze the market trend of this technology.

Topics:

Market Analysis of 3DIC
Approaches Overview of 3DIC Integration
New Materials in 3DIC Integration
Testing of 3DIC Integration
Modeling of 3DIC Integration
Roadmap Discussion of 3DIC in China
Challenges of 3D IC Development in China
EDA Tools Support for 3DIC
Panel Discussion

Who Should Attend

Executives, Experts, engineers, researchers, scholars related to auto-motive electronics design, manufacturing and service

Agenda 

Conference Host: TBD
   
8:30-9:00 Registration
   
9:00-9:10
Opening Remark

Denny McGuick
President & CEO, SEMI
   
9:10-9:40
3D Integration: where is that killer app?

Subramanian S. Iyer
IBM Fellow and Chief Technologist at the Microelectronics Division, IBM Systems & Technology Group
   
9:40-10:10
Electrical,Thermal and Mechanical Characterizations

Nozad Karim
Vice President, Amkor 
Nozad.Karim@amkor.com
   
10:10-10:40
Test Strategies for memory interfaces in 3D-IC

Gregory Smith
General Manager, Teradyne Computing & Communications Business Unit

heidi.li@teradyne.com
   

10:40-11:10

Electrical,Thermal and Mechanical Characterizations

Shiuh-Wuu Lee
Sr. VP, Technology Research & Development, SMIC


slides download

   
11:10-11:40
3D-SiP at Center Stage of Post-PC era

Walter Jau
Director, Corporate R&D, ASE Group

http://www.aseglobal.com/en/
   
13:00-13:30
 

Challenges faced by wet process in 3D TSV application

ACM David H. Wang
CEO, ACM

stella.yang@acmrcsh.com

   

13:30-14:00

ATE solutions to 3DIC test challenges: The Readiness of Advantest’s V93000

Kelvin Xia
Senior director, Phd Business Strategy Development Department, Advantest

kelvin.xia@advantest.com

   
14:00-14:20 Tea Break
   
14:20-14:50
Sputtering Application in Advanced Packaging

Dr. Ding Peijun
VP Beijing NMC Co., Ltd.

zhangx@bj-nmc.cn
   
14:50-15:20
3D Interconnect Plating Developments -Opportunities and Challenges

Dr. Zhen Qiu Liu

Director of Wet Process Engineering, TEL NEXX, Inc. USA
zhenqiu.liu@tel.com
   
15:20-15:50
TSV Technology and its Application

Dr. Daniel SHI
R&D Director, ASTRI (Hong Kong Applied Science & Technology Research Institute)
   
15:50-16:20
US Patent Topology in 3DIC Technologies and Licensing Considerations

Sherry Wu
Attorney-at-Law, Finnegan, Henderson, Farabow, Garrett & Dunner, LLP

 
slides download
   
16:20-16:50
3DIC & 2.5D Interposer market trends and technological evolutions

Pascal Viaud
CTO, Yole Développement, Taiwan Office


slides download



Contact us:

Program Manager:
Mr. Kevin Wu
Tel:86.21.6027.8558
Email:kwu@semi.org

Mr.Norman Cheng 
Tel:86.21.6027.8557
Email:ncheng@semi.org

Customer Service:
Mr. Norman Cheng
Tel:86.21.6027.8557
Email:ncheng@semi.org