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Steven Zhang(Haiyang Zhang), received his B.S., M.S. and Ph.D. degrees from Peiyang University, Tianjin, China, in 1991, 1994 and 1997, respectively and Ph. D degree in advanced process control of dry etching process from University of Houston, Texas, USA, in 2002, all in chemical engineering.
Since May, 2004, he has been with Technology R&D/micro-patterning/etch group of Semiconductor Manufacturing International (Shanghai) Corp, China. He spent more than seven years on start-up, development, optimization and transfer of 90nm logic spacer and contact etch on 200mm wafers at Shanghai (one year), 65nm logic Si-etch and 65nm logic BEOL etch on 300mm wafers at Beijing (three years) and 45/40nm logic BEOL etch on 300mm wafers at Shanghai (two years). He was ever involved in the crucial technique R&D of 90nm-65nm ultra-scale semiconductor manufacturing, the construction and verification of 65nm logic technology platform on 300mm semiconductor manufacturing tools, the R&D of 65-45-32nm semiconductor manufacturing processes and sub32nm double patterning technique.
Currently as a senior manager, he is focusing on the R&D of 32nm/28nm logic BEOL etch and SoC BEOL etch such as 45nm PC-RAM. He is presently the author and/or co-author of 50 patents and 20 dry etching related technical papers.
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