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Chinese
2017年3月14-16日
上海新国际博览中心

CSTIC 2018 Agenda

 

Plenary Session

Date: CSTIC 2018, Sunday, March 11, 2018

Venue: SHICC 上海国际会议中心 中国上海浦东滨江大道2727号

Distinguished Conference Keynote Speakers

 
Prof. Chenming Hu PR (Chidi) Chidambaram Dr. Kevin Zhang  
FinFET Inventor
Microelectronic Scientist
Vice President
QCT Process Technologies & Foundry Engineering

Qualcomm, Incorporated
Vice President
Design & Techonology Platform

TSMC
 

 

Meeting Room 3rd Floor Auditorium


08:45–09:30 Opening Ceremony
  Opening Remarks by Conference Chair
  Opening Remarks by SEMI

Opening Remarks by IMEC
  Opening Remarks by Chinese Government Representatives
  Presentation of SEMI Best Student Paper Awards and SEMI Best Young Engineer
  Paper Awards


09:30 –10:10 Role of semiconductor technology in upcoming VLSI system scaling opportunities
  PR (Chidi) Chidambaram
  Vice President, QCT Process Technologies & Foundry Engineering, Qualcomm, Incorporated
   
10:10–10:25 Coffee Break
   
10:25–11:05 TBD
 
   
11:05–11:35

TBD

 

   
11:35–12:05 TBD
 
   
12:05–13:30 1st Floor Mandarin Hall


Panel Discussion

What are the potential yield killers and their solutions of 14nm to 7nm node technologies?

Sunday, March 11, 2018

Meeting Room: 3B

17:00-18:30
 

Parallel Symposium Oral Sessions

Sunday, March 11, 2018
13:30-18:00 Parallel Symposium Oral Sessions
   
Coffee Break Conference Poster Session
   
Monday, March 12, 2018
8:00-18:00 Parallel Symposium Oral Sessions
   

 

Training Tutorial
Course 1 Devices, process integration, key modules and defects reduction for a manufacturable 14nm to 10nm CMOS technology
   
Course 2 Advanced IC Packaging and Reliability
Monday, March 12th, 2018

14:30–16:00

IC Packaging Technology Development – Current Status and Trend
Dr. Yifan Guo, Vice President of Engineering, ASE Shanghai
16:00–17:30 IC Packaging Reliability
Alex Xu, Deputy General Manager of Quality Test Center, Jiangsu Changjiang Electronics Technology Co., Ltd (JCET)



Joint Sessions

Symposium II and Symposium III-Lithograpy/Etch joint session
Sunday, March 11, 2018

Shanghai International Convention Center

Meeting Room: 3rd Floor Yellow River Hall黄河厅
Session Chairs: Kafai Lai (IBM) and Ying Zhang (Applied Material)

13:30-13:35 Opening Remarks
  Kafai Lai / Ying Zhang
**13:35-14:05 TBD
  TBD
**14:05-14:35 Patterning Roadmap
  Rich Wise, Lam Research
**14:35-15:05 TBD
  TBD
**15:05-15:35 Patterning challenges and opportunities for Advanced Memory Technology
  Gill Lee, AMAT
15:35-15:50 Coffee Break
   


Symposium II and Symposium IX-DTCO Joint session
Monday, March 13, 2017

Shanghai International Convention Center

Meeting Room: 3rd Floor Yellow River Hall黄河厅
Session chairs: Leo Pang / Yiyu Shi


*8:30-8:35 Opening Remarks
  Leo Pang / Yiyu Shi
**8:35-9:05 Design Technology Co-optimization for Disruptive Patterning Schemes
  Puneet Gupta, UCLA
**9:05-9:35 Software Defined Chip: Technologies, Challenges and Opportunities
  Shaojun Wei, Tsinghua University
*9:35-9:55 Data Analytics and Machine Learning for Design-Process-Yield Optimization in Electronic Design Automation and IC Semiconductor Manufacturing
  Luigi Capodieci, Motovi.ai
9:55-10:10 Coffee Break
   


Symposium I: Device Engineering and Memory Technology

Symposium II: Lithography and Patterning

Symposium III: Dry &Wet Etch and Cleaning

Symposium IV: Thin Film, Plating and Process Integration

Symposium V: CMP and Post-Polish Cleaning

Symposium VI: Metrology, Reliability and Testing

Symposium VII: Packaging and Assembly

Symposium VIII: MEMS, Sensors and Emerging Semiconductor Technologies

Symposium IX: Circuit Design, Systems and Applications  
  

Conference Banquet

Sunday, March 12, 2017
Banquet fee



800RMB/Person
Online Registration link;
http://121.41.226.59/semi2017/Visitor/Conference.aspx?lang=zh-chs&uid=

18:30 – 20:00 Conference Banquet, 上海小南国国会店(http://www.xnggroup.com)
上海市浦东新区滨江大道2727号7楼



Hotel Floor Layout