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March 20-22, 2019
Shanghai New International Expo Centre

CSTIC 2018 Agenda

 

Plenary Session

Date: CSTIC 2018, Sunday, March 11, 2018

Venue: Shanghai International Convention Center 上海国际会议中心 中国上海浦东滨江大道2727号

Distinguished Conference Keynote Speakers

Prof. Chenming Hu Dr. PR (Chidi) Chidambaram Dr. Kevin Zhang Dr. Zhiyong Ma
FinFET Inventor
Microelectronic Scientist
Vice President
QCT Process Technology & Foundry Engineering

Qualcomm, Incorporated
Vice President
Business Development

TSMC
Vice President
Technology & Manufacturing Group

Intel

 

Meeting Room 3rd Floor Auditorium


08:45–09:30 Opening Ceremony
  Opening Remarks by Conference Chair
  Opening Remarks by SEMI 
  Opening Remarks by IMEC
  Presentation of SEMI Best Student Paper Awards and SEMI Best Young Engineer
  Paper Awards


09:30 –10:15 Will Scaling End? What then?
  Prof. Chenming Hu
  FinFET Inventor, Microelectronic Scientist
   
10:15–10:50 Role of semiconductor technology in upcoming VLSI system scaling opportunities
  Dr. PR (Chidi) Chidambaram
  Vice President, QCT Process Technology & Foundry Engineering, Qualcomm, Incorporated
   
10:50–11:25

Driving Future CMOS Technology Scaling with Process-Design Co-Optimization

  Dr. Kevin Zhang
  Vice President, Design & Technology Platform, TSMC
   
11:25–12:00 Enabling Materials Innovations for Technology Scaling and Heterogeneous Integration
  Dr. Zhiyong Ma
  Vice President, Technology & Manufacturing Group, Intel
 
   
12:00–13:30 1st Floor Mandarin Hall


Panel Discussion

What are the yield killers and the solutions of 14nm to 7nm node technologies?

Sunday, March 11, 2018

Meeting Room: 3rd Floor Yellow River Hall 

17:00-18:30
 

Parallel Symposium Oral Sessions

Sunday, March 11, 2018
13:30-18:00 Parallel Symposium Oral Sessions
   
Coffee Break Conference Poster Session
   
Monday, March 12, 2018
8:00-18:00 Parallel Symposium Oral Sessions
   

 

Training Course
Tutorial 1 Devices, process integration, key modules and defects reduction for a manufacturable 14nm to 10nm CMOS technology
   
Tutorial 2 Advanced IC Packaging and Reliability



Joint Sessions

Symposium II and Symposium III-Lithography/Etch joint session
Sunday, March 11, 2018

Shanghai International Convention Center

Meeting Room: 3rd Floor Yellow River Hall
Session Chairs: Kafai Lai (IBM) and Ying Zhang (Applied Material)

13:30-13:35 Opening Remarks
  Kafai Lai / Ying Zhang
**13:35-14:05 Patterning Roadmap
  Rich Wise, Lam Research
**14:05-14:35 Patterning challenges and opportunities for Advanced Memory Technology
  Gill Lee, AMAT
*14:35-14:55 Desirable material selection on Self-aligned Multi-patterning
  Hidetami Yaegashi, TEL
14:55-15:10 Coffee Break
   



Symposium II and Symposium IX-DTCO Joint session
Monday, March 12, 2018

Shanghai International Convention Center

Meeting Room: 3rd Floor Yellow River Hall
Session Chairs: Leo Pang / Yiyu Shi

8:30-8:35 Opening Remarks
  Leo Pang / Yiyu Shi
**8:35-9:05 Close – loop – design and manufacturing optimization for advanced nodes

Steffen Schulze, Mentor Graphics
**9:05-9:35 Machine Learning for Lithography and Physical Design
  David Pan, University of Texas Austin
**9:35-10:05 Novel Approaches to Circuit Timing
  Ulf Schlicthmann, Technical University of Munich
10:05-10:20 Coffee Break
   


Symposium I: Device Engineering and Memory Technology

Symposium II: Lithography and Patterning

Symposium III: Dry &Wet Etch and Cleaning

Symposium IV: Thin Film, Plating and Process Integration

Symposium V: CMP and Post-Polish Cleaning

Symposium VI: Metrology, Reliability and Testing

Symposium VII: Packaging and Assembly

Symposium VIII: MEMS, Sensors and Emerging Semiconductor Technologies

Symposium IX: Design and Automation of Circuits and Systems  
  

Conference Banquet

Sunday, March 11, 2018
Banquet fee



800RMB/Person
Online Registration link;
http://semi.expotec.com.cn/Visitor/Conference.aspx?lang=en&uid=

18:30 – 20:00 Conference Banquet, 上海小南国国会店(http://www.xnggroup.com)
上海市浦东新区滨江大道2727号7楼



Hotel Floor Layout