Symposium V: CMP and Cleaning
Symposium Committee
Symposium V: CMP and Cleaning
CMP has been an enabling technology in IC manufacturing since early 1990s, and the technology continues to play critical roles with increasing applications. And Wafer cleaning, is emerging as one of the top major engineering challenges for manufacturing GAA FETs and 3D-ICs. Our CMP and cleaning knowledge at the fundamental level often reveals refreshing insights as we approach the sub-20nm or even sub-10nm technology node in the shrinking geometry while we also stack up the IC in the 3D dimension. CSTIC CMP and cleaning session (Session V) is a forum for the scientists and engineers to share all the aspects of CMP fundamentals, the latest progress in CMP and wet cleaning equipment, CMP and cleaning related materials, new CMP applications, process optimization, reliability and yield improvement.
Topics include but are not limited to the following:
1. CMP fundamentals and modeling
2. Equipment and metrology for process control and defect reduction
3. Consumables including abrasive particles, slurries, pads, conditioning disks, CMP cleaning chemicals, and brushes, etc
4. CMP and post CMP cleaning process optimization in front end, middle end, back end, and various substrates such as silicon wafers and wafer reclaiming
5. Emerging applications for 3D IC’s such as FinFET, 3D NAND, hybrid bonding, TSV, MEMS, and advanced packaging
6. Wet etching and cleaning in advanced logic and memory devices, such as GAA, advanced DRAM capacitors and 3D NAND
Symposium Committee
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Dr. Xinping Qu Chair |
Fudan University, China |
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Dr. Yuchun Wang Co-Chair |
Anji Microelectronics, China |
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Dr. Jingxun Fang Co-Chair |
Huali Microelectronics Corporation, China |
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Dr. Jin-Goo PARK Member |
Hanyang University, Korea |
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Dr. Shoutian Li Member |
Anji Microelectronics, China |
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Dr. XinChun Lu Member |
Tsinghua University , China |
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Dr. Chao-Chang Arthur Chen Member |
NTUST, Taiwan, China |
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Dr. Baoguo Zhang Member |
Hebei University of Technology, China |
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Dr. Yonggen He Member |
GrandiT Co., Ltd., China |
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Dr. Jie Cheng Member |
China University of Mining and Technology-Beijing |
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Dr. Yurong Que Member |
Shanghai Huali Integrated Circuit Manufacturing Corporation. |
Symposium V: CMP and Cleaning
CMP has been an enabling technology in IC manufacturing since early 1990s, and the technology continues to play critical roles with increasing applications. And Wafer cleaning, is emerging as one of the top major engineering challenges for manufacturing GAA FETs and 3D-ICs. Our CMP and cleaning knowledge at the fundamental level often reveals refreshing insights as we approach the sub-20nm or even sub-10nm technology node in the shrinking geometry while we also stack up the IC in the 3D dimension. CSTIC CMP and cleaning session (Session V) is a forum for the scientists and engineers to share all the aspects of CMP fundamentals, the latest progress in CMP and wet cleaning equipment, CMP and cleaning related materials, new CMP applications, process optimization, reliability and yield improvement.
Topics include but are not limited to the following:
1. CMP fundamentals and modeling
2. Equipment and metrology for process control and defect reduction
3. Consumables including abrasive particles, slurries, pads, conditioning disks, CMP cleaning chemicals, and brushes, etc
4. CMP and post CMP cleaning process optimization in front end, middle end, back end, and various substrates such as silicon wafers and wafer reclaiming
5. Emerging applications for 3D IC’s such as FinFET, 3D NAND, hybrid bonding, TSV, MEMS, and advanced packaging
6. Wet etching and cleaning in advanced logic and memory devices, such as GAA, advanced DRAM capacitors and 3D NAND