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Ravi Mahajan is an Intel Fellow responsible for Assembly and Packaging Technology Pathfinding for future silicon nodes. Ravi also represents Intel in academia through research advisory boards, conference leadership and participation in various student initiatives.
Ravi has led efforts to define directions for package architecture, technologies and assembly processes at Intel since 2000, spanning 90nm, 65nm, 45nm, 32nm, 22nm and 7nm silicon. Earlier in his Intel career, he was an individual contributor and group manager of a team responsible for thermal and mechanical solutions, tools and analysis. In that role, Ravi developed and managed a Thermal-Mechanical Lab chartered with delivering detailed thermal and mechanical characterization of Intel's packaging solutions for current and future processors.
A prolific inventor and recognized expert in microelectronics packaging technologies, Ravi holds more than 40 patents, including the original patents for silicon bridges that became the foundation for Intel's EMIB technology. His early insights have also led to high-performance, cost-effective cooling solutions for high-end microprocessors and the proliferation of photo-mechanics techniques used for thermo-mechanical stress model validation. Ravi has written several book chapters and more than 30 papers on topics related to his area of expertise.
Ravi joined Intel in 1992 after earning a Bachelor's degree from the University of Bombay (1985), a Master's degree from the University of Houston (1987), and a Ph.D. from Lehigh University (1992), all in mechanical engineering. His contributions during his Intel career have earned him numerous industry honors, including the SRC's 2015 Mahboob Khan Outstanding Industry Liaison Award, the 2016 THERMI Award from SEMITHERM, the 2016 Allan Kraus Thermal Management Medal & the 2018 InterPACK Achievement award from ASME and IEEE Region 6 & Phoenix Section 2019 “Outstanding Service and Leadership to the IEEE” Award. He is an IEEE EPS Distinguished Lecturer. He is one of the founding editors for the Intel Assembly and Test Technology Journal (IATTJ) and currently VP of Publications & Managing Editor-in-Chief of the IEEE Transactions of the CPMT. Additionally he has been long associated with ASME's InterPACK conference and was Conference Co-Chair of the 2017 Conference. Ravi is a Fellow of two leading societies, ASME and IEEE. He was named an Intel Fellow in 2017.
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