** to designate keynote talk - 30 min      
* to designate invite talk - 25 min
  to designate regular talk - 20 min

Monday, June 26, 2023 Shanghai International Convention Center
Meeting Room: 3rd Floor Yellow River Hall

Session I: Advanced Device and Technology for Intelligent Chips
Session Chair: Zhongrui Wang
**13:30-14:00 Bioinspired in-sensor computing for artificial vision
  Yang Chai, HK Polytechnique University
*14:00-14:25 Architectures and Chips of "Sensing with Computing" for Intelligent Continuous Perception
  Fei Qiao, Tsinghua University
*14:25-14:50 High Density Integrated Intrinsically Stretchable Electronics
  Yuqing Zheng, Peking University
*14:50-15:15 2D NEMS and 2D Electronics for Energy-Efficient Sensing and Computing
  Rui Yang, Shanghai Jiao Tong University
15:15-15:30 Coffee Break
   

Session II: In-Memory Compute Technologies
Session Chair: Fei Qiao
*15:30-15:55 Memristor-based Reservoir Computing
  Zhongrui Wang, University of Hong Kong
*15:55-16:20 In-Memory Computing for Machine Intelligence
  Bonan Yan, Peking University
*16:20-16:45 Low Carbon Chips for Emerging Zeta-scale Computing
  Hao Yu, Southern University of Science and Technology
*16:45-17:10 Hardware-Based Neural Networks Using Flash Memory Technologies
  Sungmin Hwang, Korea University Sejong Campus
17:10-17:25 Design of Ferroelectric FET-Based Capacitive-Coupling Computing-In-Memory for Binary Neural Networks
  Boyi Fu, Peking University
17:25-17:40 HFXZR1-XO2 FERROELECTRIC THIN FILM GRAIN SIZE TUNING VIA ANNEALING RAMP RATE ACHIEVING ENDURANCE >10^9 CYCLES, 2PR OF 40.6 µC/CM^2, WRITE VOLTAGE DOWN TO 1.5 V, AND SWITCHING SPEED OF 30 NS
  Jun Lan, Southern University of Science and Technology
   

Tuesday, June 27, 2023 Shanghai International Convention Center
Meeting Room: 3rd Floor Yellow River Hall


Session III: Device and Technology
Session Chair: Bonan Yan
**8:30-9:00 Hybrid 2D/CMOS Microchips for Memristive Applications
  Mario Lanza, King Abdullah University of Science and Technology (KAUST)
*9:00-9:25 High Performance Electronic Devices Based on Novel Materials for Logic and Memory Applications
  Yanqing Wu, Peking University
*9:25-9:50 Ferroelectric Devices as Next Generation Low-Power Logic Technology: NCFETs
  Sihyun Kim, Sogang University, Korea
*9:50-10:15 Functional circuits based on 2D semiconductors
  Wenzhong Bao, Fudan University
10:15-10:30 Large Area CVD MoS2 Memristor Suitable For Neuromorphic Applications
  Xuewei Feng, Shanghai Jiao Tong University
10:30-10:45 The Study on Reducing Bit line Parasitic Capacitance in Advanced DRAM
  Yexiao Yu, ChangXin Memory Technologies
10:45-10:55 Coffee Break
   

Session IV: Advanced Device Technology
Session Chair: Hao Yu
*10:55-11:20 Low Temperature Ge CMOS for Future M3D Technology
  Heng Wu, Peking University
11:20-11:35 Technologies for Superior Reliability in SiC Power Devices
  Min-hwa Chi, Micro-Nano Technology College, Qingdao University
11:35-11:50 Leakage Reduction of GAA Stacked Si Nanosheet CMOS Transistors and 6T-SRAM Cell via Spacer Bottom Footing Optimization
  Xuexiang Zhang, Institute of Microelectronics, Chinese Academy of Sciences
11:50-12:05 Experimental Investigation of Ultra-low Temperature La2O3/HfO2 Bi-layer Dipole-first Process Using PVD Method for Advanced IC Technology
  Yanzhao Wei, Institute of Microelectronics, Chinese Academy of Sciences
12:05-12:20 A Compact Sawtooth Wave Generator Based on Novel Z²-Fet Device
  Hui Xie, Fudan University
12:20-13:30 Lunch Break
   
Poster Session:
  Fabrication and Characterization of a Novel Embedded Mirror Gate SONOS
  Ning Wang, Shanghai Huahong Grace Semiconductor Manufacturing Corporation
  High endurance SONOS technology improved by design &process optimization
  Pingsheng Zhou, Shanghai Huahong Grace Semiconductor Manufacturing Corporation
  Promoting Chip Probing Test Yield by Simple ISSG and Global Wet Process
  Jingsong Peng, Shanghai Huahong Grace Semiconductor Manufacturing Corporation
  An On-chip Superconducting Quantum Transponder
  Rutian Huang, Tsinghua University
  Design and simulation of a superconducting switch based on weakly damped superconducting quantum interference devices
  Xinyu Wu, Tsinghua University
  55NM ULTRA LOW LEAKAGE PLATFORM DEVELOPMENT
  Yifan Ding, Shanghai Huali Microelectronics Corporation
  Optimization of crack in active area on 50 nm ETOX NOR Flash
  Jiayu Ma, Shanghai Huali Integrated Circuit Corporation
  RESEARCH ON VT WINDOW IMPROVEMENT PROCESS OF 2T SONOS EMBEDDED FLASH
  Xiaokang Li, Shanghai Huali Microelectronics Corporation
  RESEARCH ON VT WINDOW IMPROVEMENT PROCESS OF SONOS EFLASH IN COMBINATION WITH 55NM ULTRA-LOW POWER LOGIC TECHNOLOGY
  Wencan Xu, Shanghai Huali Microelectronics Corporation
  An Effective Method to Minimize the Difference between Spot and Ribbon Beam by Co-implantation
  Long Feng, Semiconductor Manufacturing North China (Beijing) Corp.
  Study of Breakdown Voltage improvement of High-voltage PLDMOS
  Wenting Duan, HuaHong Grace Semiconductor Manufacturing Corporation
  The Optimization of the specific on-resistance of 60V shield gate trench MOSFET with low doped epitaxial layer
  Xiaoqing Cai, HuaHong Grace Semiconductor Manufacturing Corporation
  A Better Al Filling Gate Mass-Production Technology at 28 nm High-K/Metal Gate CMOS
  WenZhao Fu, Shanghai Huali Integrated Circuit Corporation
  Study of the formation of Copper void defect and process optimization for reduction in dual damascene process
  Hongliang Zhu, Semiconductor Manufacturing International Corporation
  Study on N-Type MOSCAP Capacitor and Range in 55nm CMOS
  Hongliang Zhu, Semiconductor Manufacturing International Corporation
  Research on Performance Improvement of 40V NEDMOS
  Chongkai Du, Shanghai Huali Microelectronics Corporation
  INVESTIGATION OF A NEW DISTURB EFFECT IN THE AGGRESSIVELY SCALED DUAL-BIT/CELL SPLIT-GATE FLOATING-GATE FLASH CELL
  Zhaozhao Xu, Huahong Semiconductor (Wuxi) Limited
  Important Process Parameter and Its Sensitivity Check by Virtual Fabrication: Channel Hole Profile Impact on Advanced 3D NAND Structure
  Qingpeng Wang, Coventor, Inc., A Lam Research Company
  FinFET Source/Drain Parasitic Resistance Optimization by TCAD Simulation
  Tongtong Luan, ShanghaiTech University
  Simulation Study of Gate-All-Around Nanosheet Devices Based on SOI Structure
  Yangyang Hu, Shanghai University
  Full Well Capacitance of Small Size CMOS Image Senor:Improvement and stability control
  Xiaoyu Li, Shanghai Huali Microelectronics Corporation
  Investigation of electrical characteristics on Morphotropic Phase Boundary of Hf1-xZrxO2 for Dynamic Random Access Memories
  Kun Zhong, Institute of Microelectronics, Chinese Academy of Sciences
  Investigation of the doping profile for ion implants and rapid annealing in silicon via an improved method
  Zeqi Zha, Semiconductor manufacturing International (Beijing) Corporation
  Novel Channel-On-Fin (COF)IGZO-TFTs with Ultra-Scaled Back Gate Length of 23 nm
  Shangbo Yang, Institute of Microelectronics, Chinese Academy of Sciences
  Investigation of vertical channel IGZO-TFT based on PVD-IGZO
  Zhiyu Song, Institute of Microelectronics, Chinese Academy of Sciences
  A Compact Model of Non-volatile Ferroelectric Tunnel FET with Ambipolarity for In-memory-computing
  Hanyong Shao, Peking University
  Investigation of Synergic Hydrogen Mitigation Technique for Top-Gate a-IGZO Thin-Film Transistors
  Gangping Yan, Beijing Superstring Academy of Memory Technology
  Characterization of Field Cycling Fatigue in HfZrOx Ferroelectric Capacitors
  Puyang Cai, Peking University
  Reliability Performance of Novel Tunneling Field Effect Transistors Based on Foundry Platform
  Yukun Tang, Shanghai Jiaotong University
  Mechanism and data fusion characterization of Si-doped c-BAs
  Chun Wang, Northeastern University
  A Method for Sharp Corner Rounding of Active Area to Improve the Reliability of 2Xnm NAND Flash Devices
  Zhiguo Li, Semiconductor Manufacturing International Corporation
  Predicting Iread Worst-Case Corner of SRAM based on Statistical Probability
  Zongkang Zeng, Semiconductor Manufacturing International Corporation
  Methods of Fast Prediction for the Worst Iread using Confidence Interval
  Chaoyue Qu, Semiconductor Manufacturing International Corporation
  Influence of Interfacial Layers and High-k Post Dielectric Annealing on the Characteristics of MOS Devices
  Guanqiao Sang, Institute of Microelectronics, Chinese Academy of Sciences
  Optimized Wafer Edge Condition in Lithographic Process For Peeling Defect Improvement in 28nm Technology
  Shanshan Chen, Shanghai Huali Integrated Circuit Corporation
  SILICIDE PROFILE OPTIMIZATION ON ACTIVE AREA IN 4XNM ETOX NOR FLASH MEMORY
  Yuxin Tong, Shanghai Huahong Grace Semiconductor Manufacturing Corporation
  Improvement of Standby current failure by device optimization on 4Xnm ETOX NOR-flash memory
  Zhuangzhuang Wang, Shanghai Huahong Grace Semiconductor Manufacturing Corporation
  Effects of floating gate profile on Cell Characteristics of 4Xnm FG-first ETOX NOR-flash memory
  Yihang Du, Shanghai Huahong Grace Semiconductor Manufacturing Corporation
  Improved Environmental Stability of N-type Polymer Field-Effect Transistors using Nickel Contact Electrodes
  Yuan Liu, Nanjing University of Posts and Telecommunications
  A New Method to Calculate Loading Effect in Embedded Flash
  Fangce Sun, HuaHong Grace Semiconductor Manufacturing Corporation
  A New Method to Improve Split Gate Flash Erase and Endurance
  Fangce Sun, HuaHong Grace Semiconductor Manufacturing Corporation