(** to designate keynote talk, * to designate invite talk)

Sunday, March 12, 2017 Shanghai International Convention Center
Meeting Room: 3B

Session I: Memory Technology - I
Session Chair: Min-Hwa Chi


**13:30-14:00 STT-MRAM and its Application for Nonvolatile Brain-Inspired VLSIs
  Tetsuo Endoh, Tohoku University
**14:00-14:30 Perpendicular STT-MRAM Macro Embedded into 40nm CMOS Logic Platform
  Yu Lu, Hikstor Technology Ltd.
**14:30-15:00 Diffusive Memristors for Future Computing
  Jianhua Yang, University of Massachusetts
*15:00-15:25 Ultrathin Bilayer Nonlinear RRAM based on Non-filamentary Switching Mechanism
  Tuo-Hung Hou, National Chiao Tung University
15:25-15:40 Coffee Break
   

Session II: Novel Solid State Devices
Session Chair: Cor Claeys


**15:40-16:10 III-N Heterostructure Devices for Low-Power Logic
  Patrick Fay, the University of Notre Dame
*16:10-16:35 Steep Slope Transistors with tunnel FETs for Low Power Electronics
  Qingtai Zhao, Forschungszentrum Julich
*16:35-17:00 Monolithic 3D (M3D) Reconfigurable Logic Applications Using Extremely-Low-Power Electron Devices
  Woo Young Choi, Sogang University
   
Poster Session: Location: Foyer of Yangtze River Hall
Coffee Break A Method to Solve Reverse Tunneling Disturb Issue for Split-Gate Super Flash Memory
  Tao Xu, Shanghai Huahong Grace Semiconductor Manufacturing Corporation
  The Design and Implementation of A Reconfigurable Convolution Operator based on APU
  YuQian Huang, Peking University
  Compact Electrodynamics MEMS-Speaker
  Burhanuddin Yeop Majlis, Universiti Kebangsaan Malaysia
  IDENTIFICATION AND SOLUTIONS FOR A NOVEL PARTICULATE POLLUTION MATTER IN WAFER SURFACE CAUSED BY CONCENTRATED SULFURIC ACID
  LU SUN, SMIC
  Optimal Experiment Design in Poly Etch Process for Performance Improvement on Different Type Tool
  Ying Emily Lu, Semiconductor Manufacturing International Corporation
  Development of damage free megasonic cleaning device
  Yu Teng, Beijing NAURA Microelectronics Equipment Co., Ltd.
  A Reliability Study of A New Embedded Flash to Reduce Charge-Loss Issue
  Lingling Shao, SMIC
  IDLE RECIPE AUTOMATIC CONTROL
  Wei Wei Yan, Semiconductor Manufacturing International Corporation
  Investigation of CMOS Image Sensor Dark Current Reduction by Optimizing Interface defect
  Wu Zhi Zhang, Shanghai Huali Microeletronics Corporation
  A Novel 25V DDD NMOS Design in 500-700V Ultra High Voltage BCD Process
  Donghua Liu, Shanghai Huahong Grace Semiconductor Manufacturing Corporation
  Metal-electrode-dependent negative photoconductance response of the nanoscale conducting filament in the SiO2-metal stack
  Tomohito Kawashima, Toshiba
  A Novel 25V PLDMOS Design in 700V BCD Process
  Wenting Duan, Shanghai Huahong Grace Semiconductor Manufacturing Corporation
  The Vt Variation Improvement by SuperScan II in PMOS Device
  Xiaoqi Li, Applied Materials China
  Application of resist profile model and resist-etch model in solving 28nm Metal resist toploss
  Tan Yiqun, Shanghai Huali Microelectronics Corporation
  Depletion-Mode MOS Capacitor Modeling Investigation
  Chien-Lung Tseng, SMIC
  Simulation on the Performance Comparison for Nanoscale SOI and Bulk Junctionless FinFETs
  Cheng-Kuei Lee, Tsinghua University
  Analysis and Modeling of Self-Heating Effects in Bulk FinFETs
  Xi Lin,SMIC ATD


Monday, March 13, 2017 Shanghai International Convention Center
Meeting Room:Meeting Room: 3B

Session III: Device Reliability and Noise Characteristics
Session Chair: Huaqiang Wu


8:30-8:45 A Study of HCI Improvement by 28nm LDMOS Structure Optimization
  Ruoyuan Li, SMIC
8:45-9:00 Reliability Investigations on The Programming Currents of 28nm Metal E-Fuse
  Guangyan Zhao, SMIC
9:00-9:15 Physics-Based Analytical Modeling for Electromigration Reliability in Multi-Branch Interconnect Trees Considering Time-Varying Temperature
  Jiangtao Peng, Shanghai Jiao Tong University
**9:15-9:45 Reliability Enhancement of Phase Change Memory Using Metal Nitride Liner
  SangBum Kim, IBM
*9:45-10:10 Defects and Lifetime Prediction for Ge pMOSFETs under AC NBTI Stresses
  J.F.Zhang, Liverpool John Moores University
10:10-10:25 Coffee Break
   

Session IV: Memory Technology - II
Session Chair: Chung Lam


**10:25-10:55 Challenges and Opportunities for RRAM: From Technology to Applications
  Zhiqiang Wei, Panasonic
*10:55-11:20 Investigation of Trap Profile in Nitride Charge Trap Layer in 3-D NAND Flash Memory Cells
  Jong-Ho Lee, Seoul National University
11:20-11:35 Spike Timing Dependent Plasticity of Flexible and Fully Transparent Memristors for Electronic Synapse Applications
  Chenghao Liao, Fuzhou University
11:35-13:05 Lunch Break
   

Session V: 1D and 2D Material
Session Chair: Jong-Ho Lee


*13:05-13:30 Nanoscale Thermocapillarity Enabled Purification For Horizontally Aligned Arrays of Single Walled Carbon Nanotubes
  Sung Hun Jin, Incheon National University
*13:30-13:55 High Performance Two Dimensional Electronic Devices
  Yanqing Wu, Huazhong University of Science and Technology
*13:55-14:20 Analyzing the carrier mobility in two-dimensional MoS2 transistors
  Xinran Wang, Nanjing University
14:20-14:35 Coffee Break
   

Session VI: Advanced Device and Process Technology
Session chair: Hong Wu


*14:35-15:00 Advanced Logic and Specialty Technologies for VLSI Manufacturing in fast expansion at China
  Min-hwa Chi, SMIC
*15:00-15:25 Comparative Experimental Study of the Improved MOSFET Matching by Using the Hexagonal Layout Style
  Salvador Pinillos Gimenez, Centro Universitario da FEI
15:25-15:40 Analytical Modeling for Substrate Effect of Lateral Power Devices
  Yufeng Guo, Nanjing University of Posts and Telecommunications
15:40-15:55 MOSFET RF Performance Improvement through Spacer Profile Optimization for 28nm Poly/SiON SOC Technology
  Hai Liu, SMIC
15:55-16:10 Highly Precise Control of Poly Gate etching by Interferometry Endpoint Prediction (IEP)
  Jie Zhang, AMEC
16:10-16:25 Analysis of Temperature Effects for 14nm FinFET Technology
  Xiaolei Yang, SMIC