|
Kaitsuka Takanobu 先端半导体技术部部长，TEL |
|
个人简介 Takanobu Kaitsuka was born in 1960, in Ibaraki, Japan. He received the B.S. degree in metallurgy from Ibaraki University in 1984. He jointed Texas Instrument Japan Limited, Ibaraki, Japan, in 1984, where he worked various positions for semiconductor process development. In 1998, he joined Tokyo Electron Limited, Yamanashi, Japan, where he managed and directed characterization, process development, and feasibility study of semiconductor process. Currently he is Leader of Device Technology Project at Tokyo Electron Limited. 摘要 The advancement in latest DRAM and 3D NAND leads to tremendous process challenges such as very ultra-fine pattern formation, high aspect ratio etching, high step coverage deposition, critical cleaning, etc. Yield enhancement is also a critical item for memory manufacturers since it directly lead to production cost. In this talk, we will address how equipment technology provides additional knobs to solve above challenges through various aspects, paving the way towards the success of final product. Looking forward, we will also touch on latest emerging memory technology, new process, and material challenges they required. |
|
