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June 27-29, 2020
Shanghai New International Expo Centre

Symposium I: Device Engineering and Memory Technology


** to designate keynote talk - 30 min
* to designate invite talk - 25 min
  to designate regular talk - 15 min

Parallel Symposium Oral Sessions: June 29-July 17, 2020

Session I: Novel Device Technology
** Symmetric Lateral Bipolar on SOI – An Ideal Device Platform for Universal RAM

Tak Ning, IBM
** Nanowire & Nanosheet FETs for Advanced Ultra-Scaled, High-Density Logic and Memory Applications

Anabela Veloso, IMEC
* Stacked High Mobility Channel Transistors

CheeWee Liu, National Taiwan University
* High Temperature Applications of SiC Devices

Mikael Ostling, KTH Royal Institute of Technology
Session II: Emerging Devices and Technology
** 3D Sequential Integration: Latest Advances and Promises

Jean-Charles Barbé, CEA-LETI

*

Semiconductor Quantum Dot Devices for Quantum Computing

HongWen Jiang, UCLA

*

Emerging Low-Dimensional Materials for Memory and Computing

Han Wang, University of southern California
Session III: Advanced Memory Technology

Design of a Novel One Transistor-DRAM Based on Bulk Silicon Substrate

Kai Xiao, Fudan University

Manufacturing Challenges and Cost Evaluation of New Generation 3D NAND Memories

Dube Belinda, systemplus consulting

A New structure of ILD Gap Filling Improvement for Floating-gate Memory

Zhenghong Liu, HLMC
* Neuromorphic Technology Utilizing Flash Memory Cells

Jong-Ho Lee, Seoul National University
* Memory landscape evolution in the time of A.I.

Yangyin Chen, Western Digital
Session IV: Neuromprphic Computing Technology
** Embedded ReRAM Technology and Neuromorphic Application

Takumi Mikawa, Panasonic Semiconductor Solutions

Investigation of Multi-Level Properties of TaOx-based Memristive Devices and Optimized Programming Scheme for On-Line Training

Teng Zhang, Peking University

Neural Spike Detection Based on 1T1R Memristor

Zhengwu Liu, Tsinghua University

Implementation of Lateral Divisive Inhibition Based on Ferroelectric FET with Ultra-Low Hardware Cost for Neuromorphic Computing

Shuhan Liu, Peking University

Defect-Centric Multi-Scale Approach Simulation of Emerging Memories for Neuromorphic Applications

Andrea Padovani, Applied Materials Italy
Session V: Advanced Device Reliability
* High Yield and Superior Quality/Reliability of IGBT and Power Devices at AI Era

Min-hwa Chi, SiEn (Qingdao) Integrated Circuits Cor.
* Understanding Random Telegraph Noise (RTN) in FinFETs from Devices to Circuits

Runsheng Wang, Peking University
* True random number generator (TRNG) for secure communications in the era of IoT

Zhigang Ji, Shanghai Jiaotong University

Yield Enhancement by Virtual Fabrication: Using Failure Bin Classification, Yield Prediction and Process Window Optimization to Identify and Prevent Process Failures

Qingpeng Wang, Coventor Inc., a Lam Research Company
Session VI: Advanced CMOS Devices and processTechnology
* High-Performance TFTs Based on Semiconductors and Semi-Metals

Aimin Song, University of Manchester
* Prospect of Ultra-Thin Ferroelectric HfZrO2 for Low-Power Applications

Min-Hung Lee, National Taiwan Normal University

A Device Design for the 5 nm Logic Technology Node

Ding Yu, Shanghai IC R&D Center

Optimization of Embedded SiGe Process to Enhance PFET Performance on 28nm Low Power Platform

Xuejiao Wang, HLMC

A Study of FinFET Device Optimization and PPA Analysis at 5 nm Node

Xin Luo, Shanghai IC R&D Center

A Simple Current Test Method on Wafer Level to Pre-verify Circuit Function

Jianrong Xu, HLMC

Novel Semiconductor Devices Based on SOI Substrate

Jing Wan, Fudan University

Effect of Dissolved Ozone and In-Situ Wafer Cleaning for Pre-epitaxial Deposition for Next Generation Semiconductor Devices

Ismail Kashkoush, NAURA-Akrion, Inc.

From Microns to Nanometers: The IRDS and AMC Control

Christopher Muller, Muller Consulting

Conference Poster Session: June 26-July 17, 2020

  Effect of probe station tips pressure in the characterization of memristors
  Ying Zuo, Soochow University
  Transmission electron microscopy based quality analysis of commercially available graphene oxide quantum dots
  Biyu Guo, Soochow University

Study of Shallow Trench Isolation Gap-fill for 19nm NAND Flash
  Li Peng, Hongbo Li, Tiantuo Sun, Xing Gao, Qin Sun, HLMC

Local Mismatch Model Modeling Method for MOS Transistors
  Gu Jinglun, HLMC
  An application of LDMOS on ESD protection

Li Wang, HHGrance WUXI
  HV Gate Oxide Over-Oxidation Process Optimization for SONOS 1.5T Flash Cell

Jian Zhang, HHGrance WUXI
  Potential Applications of h-BN Crystals in Future ULSI

Guangyuan Lu, HHGrance WUXI
  Improved HCI of Embedded High Voltage EDNMOS in advanced CMOS Process

LIU JUNWEN, HHGrance WUXI
  Image Aberration Correction for Lithography Machine Illuminant based on Schmidt Corrector Plate

LiMing, Zhanglidong, HLMC
  Improved Standby Leakage of Huge Volume SRAM by Thin SIN Film of STI Liner
  Xiaobing.Ren, HHGrance WUXI

A Study of damage cause of extremely thin PR line in etch process and solution in 19NAND Process
  Zheng hongzhu; Wang Baoguang; Zhao Bin, HLMC

A Study of Plasma Damage induced floating Poly Structure OTP or MTP Reliability fail
  ChenYu, HHGrance WUXI
  Minimized junction leakage current for nanoscale MOS device applications

Wenqi Bai, HLMC
  Study of Related Yield Loss and Mechanism of NOR Flash Self-Align-Source

Zhi Tian, HLMC
  High performance HVNMOS development for advanced planner NAND flash

Juanjuan Li, Zhi Tian, Xiaohua Ju, Tao Liu, Shaokang Yao, Haewan Yang, Yaoyu Chen, HLMC
  Development of low leakage current in extreme PFET device
  Wenqi Bai, HLMC

Demonstration of the Novel Low-Power Fully Self-Aligned Split-Gate SONOS Embedded Flash
  Zhaozhao Xu, HHGrace

Investigation of Hot Carrier Effect of A Novel STI-Based n-Type LDMOS Transistors
  Zhaozhao Xu, HHGrace

A New Integration flow Study of ONO film Uniformity and Silicon recess improvement for 2T-SONOS Flash
  Liqun Dong, HLMC

Study of GIDL improvement for 2T-SONOS Flash
  Zhenghong Liu, HLMC

One new calibration structure of MOSFET gate oxide capacitor
  Han Xiaojing, HLMC

Effective approaches for SACVD particle performance improve
  Yongxiang Zhao, Applied Materials China

AMAT Preclean --- a more aggressive contact clean
  Jian Xiao, Applied Materials China

Narrow-band mask synthesis with semi-implicit difference
  Yijang Shen, Guangdong University of Technology

Wafer Edge Peeling Defect Mechanism Analysis and Reduction In IMD Process
  Feng Yali, HLMC

Evaluation of pre silicide implant from low temperature to room temperature
  Zhou Chun, HLMC

Process Control in Multi-Station PECVD Systems
  Xin Gan, Mao Sen Li, Yu Shan Chi, Lam Research (Shanghai) Co., Ltd.

Fragmentation of Square Pattern Mask with Small Corner-to-Corner Space
  Yu Shirui, Chen Yanpeng, Wang Dan, Deng Guogui, Hu Yidan, HLMC

Study of low pinch-off voltage JFET in 500V high voltage process
  Wenting Duan, HHGrace
  STUDY OF MOSFET IDVG CURVE DOUBLE HUMP EFFECT

Jun Hu, HHGrace
  Effect of implant beam current on resistance of BF2 implanted polysilicon
  Lichao Zong, HHGrace

Deep Power Down Leakage Study Caused by Poly L-shape Pattern
  Chong Huang, HHGrace
  Virtual Source for an Odd Mathieu-Gauss Beam and Compare of the Functional Images of the Odd and Even

Xuxin Qi, HLMC
  The study of 2D NAND flash CM2 etch top fence formation mechanism and solution

Qian Tao, HLMC
  Detection of Electrical Defects by distinguish methodology using an Advanced E-beam Inspection System

Shanshan Chen, HLMC
  High-density memristor crossbar arrays prepared by electron beam lithography

Shisheng Xiong, Fudan university
  Study of Ultra-high Voltage BCD Process with Gate Oxide Thinning

Donghua Liu, HHGrace
  THE METHOD OF IMPROVING ALD SICN FILM UNIFORMITY

Hao Yanxia, HLMC
  Magnetoelectric memory cell based on microsized FeGa films on ferroelectric 50BZT–50BCT films
  Zhi Tao, Tianjin University of Technology

The Effect of Fin Profile to 5nm Finfet Technology Design
  Enming Shang, Shanghai IC R&D Center
  Graphene Oxide for Nonvolatile Memory Application by Using Electrophoretic Technique

Yong Zhang, Shanghai University
  A new method to reduce Ciss of SGT MOSFET
  Yulong Yang, HHGrace

The effectively method of enhancing clean ability in Brush clean step
  Junyi Hu, Applied Materials

Applied Centura® RP EPI Tool Enhances 12-Inch
  Chengpeng QIN, Applied Materials CHINA

Advanced Remote Plasma Oxidation for Conformality Improvement on High Aspect Ratio (AR) 3D NAND Flash
  He Yang, Applied Materials China

Applied Endura® SIP TTN™ for Titanium Silicide and Contact Glue Application in 300mm Power Devices
  Qingshan Zhang, Applied Materials China

Mechanism Study of Wafer Surface Charge during Dual Damascene Process and an Effective Removal Method Using Functional Rinse
  Heguang Shi, Semiconductor Manufacturing International Corp.

A Real Time Current Monitor on Ribbon Beam Implanter
  Peng Yue, Applied Materials

AMAT PAD ETCH Chamber for High MTBC Requirement Solution
  Jing Tong, AMAT

TaOx synapse array based on ion profile engineering for high accuracy neuromorpic computing
  Yuchao Yang, Peking University
  The causation and improvement of one type of particles occurring in Batch-clean tool

Jing.Ye, Shanghai Huanhong Grace Semiconductor Manufacturing Corporation
  Impact of Nanopillar-type Electrode on HfOx -based RRAM Performance

BaoTong Zhang, Peking University
  IMPROVEMENT ON ELECTRONIC CHARACTERISTICS OF TaOx/TiOx DUAL-LAYER STRUCTURE RESIATIVE MEMORY

Yu She, Tianjin University of Technology
  An Efficient Method of SiN Residue and Divot Reduction by Integrated Process Optimization of STI CMP and Certas Etch

Zhejun Liu, Shanghai Huali Integrated Circuit Corporation
  A NOVEL GATE ARCHITECTURE DESIGN IN STI BASED LDMOS

Ziquan Fang, HuaHong Grace Semiconductor Manufacturing Corporation
  Impacts of Circuit Limit and Device Noise on RRAM Based Conditional Generative Adversarial Neural Network

Shengyu Bao, Peking University
  Implementation of Graph Convolution Network based on Analog RRAM

Daqin Chen, Peking University
  TCAD Simulation on Random Telegraphy Noise and Grain-induced Fluctuation of 3D NAND Cell Transistors

Shijie Hu, Peking University
  A PHYSICAL CURRENT MODEL FOR MULTI-FINGER GATE TUNNELING FET WITH SCHOTTKY JUNCTION

Yimei Li, Peking University
  Origin of Steep Subthreshold Swing within the Low Drain Current Range in Negative Capacitance Field Effect Transistor

Chang Su, Peking University
  Circuit Reliability Evaluation of Approximate Computing

Yuwei Zhang, Peking University
  The Plasma Assistant CD Shrinkage in Metal Gate Cut Process

Shiliang Ji, SMIC
  Device Modeling and Application Simulation of Ferroelectric-FETs with Dynamic Multi-Domain Behavior

Zhiyuan Fu, Peking University

A Novel Electrical Isolation Solution for Tunnel FET Integration
  Ting Li, Peking University