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English
March 14-16,2018
Shanghai New International Expo Centre

Zvonimir Bandic

Zvonimir Bandic
Sr. Director, Next Generation Platform Technologies, West Digital

In the last 5 years semiconductor industry has witnessed a flurry of R&D activity in the area on emerging non-volatile memories (eNVM). At component level, eNVMs are characterized by low latency, substantially similar to DRAM and much lower than NAND flash, relatively high density, and non-volatility. Their component cost is expected to be between DRAM and 3D NAND flash.

In this presentation we will consider two main programming models that can take advantage of nanosecond-scale, persistent memory components: processor addressed memory architecture model, and block I/O architecture model. We have implemented prototype devices based on both models, and measured and compared system performance with emphasis on access latency from applications’ perspective. We will discuss performance and implementation advantages and disadvantages of both approaches, and provide an assessment of software and operating system readiness.

In addition to accessing persistent memories locally, we also considered a variety of architectures for large-scale deployment of persistent memory. Accessing persistent memory devices across the network brings its own set of challenges that significantly depend on the memory architecture model, but also on the network latency. The new classes of ultrafast block memory devices are creating a challenge for distributed architecture, as network latency has to be improved and has to reach similar performance scale to utilize the new memories fully. We will discuss networking protocols (such as NVMe over fabrics), their implementation and performance, and prototype networking architectures that can reduce networking latency to sub-2us scale.