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Jin Pan CTO, Suzhou HYC Technology Co., LTD |
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Biography Patents:10 Publications : 11 1995 – 2016 Intel Corporation, Sort/Test Technology Development 2011 – 2016 Sr Principal Engineer • Lead architect for 5G wireless RF test solution; • Architected the industrys highest current device power supply (up to a few hundred amps) for in house tester; • Architected high power, highest density, massive parallel semiconductor device burn-in solutions; • Architected industrys low cost most integrated device parametric measurement instrument solutions; 2007 – 2010 Principal Engineer • Architected digital channel card and low current, medium current device power supply card and mentored design engineers for implementation and performance tuning; • Resolved thermal diode issues related to fab process and invented a thermal diode compensation algorithm. 2005 – 2006 RF/MS Test Strategy group manager • Led a small group of engineers and developed 4 different flavors of final test modules for testing Intel's Centrino WiFi baseband and RF products. Partnered with equipment development engineers and developed with vendor the highest density RF instruments (A93K 10x) at that time. 2001 – 2004 Pathfinding manager • Led a small team of 4 engineers that fundamentally re-architected the burn in system and system level test (SLT) system and made numerous improvements to the test flow and test process. 1995 – 2000 Wafer sort module development engineer, wafer sort module development group leader Developed bond pad sort probing process, completed the initial development of the Intel’s first-ever C4 probing process and 12” wafer probing system, developed Intel's first automated sort SPC/SBL system with automated response that was later on proliferated to all test steps, developed J973 structural sort module, proposed and demonstrated Electrical Z height Alignment on sort module that is still in use today. |
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