SEMICON China - 主题与特邀演讲嘉宾 (2020)

Keynote & Invited Speakers(2020)

	Next Big Frontiers - Chiplet Integration and More Dr. Doug Yu, Vice President, TSMC	Opportunities in Advanced Packaging for Heterogeneous Integration Dr. Ravi Mahajan, Fellow, Intel

	EUV Lithography - the Road to High-Volume Manufacturing Dr. Anthony Yen, Vice President, ASML	Integrated Materials Solutions: A Path Forward For Moore's Law Dr. Sanjay Natarajan, Vice President, Applied Materials

Partial List of Confirmed Distinguished CSTIC 2020 Invited Speakers

	Embedded ReRAM technology and neuromorphic application Dr. Takumi Mikawa, Senior Manager, Panasonic Semiconductor Solution	Symmetric Lateral Bipolar on SOI - An Ideal Device Platform for Universal RAM Dr. Tak H. Ning, IBM Fellow (retired)

	Nanowire & Nanosheet FETs for Advanced Ultra-Scaled, High-Density Logic and Memory Applications Dr. Anabela Veloso, Principal Member of Technical Staff, IMEC	High Yield and Superior Quality/Reliability of IGBT and Power Devices at AI Era Dr. Minhwa Chi, SVP, SiEn (Qindao) Integrated circuits

	High-Performance TFTs Based on Semiconductors and Semi-Metals Aimin Song, Professor, University of Manchester	Stacked high mobility channel transistors CheeWee Liu, National Taiwan University

	Prospect of Ultra-Thin Ferroelectric HfZrO2 for Low-Power Applications Min-Hung Lee, National Taiwan Normal University	Emerging Low-Dimensional Materials for Memory and Computing Han Wang, University of southern California

	Understanding Random Telegraph Noise (RTN) in FinFETs from Devices to Circuits Runsheng Wang, Peking University	Neuromorphic Technology Utilizing Flash Memory Cells Jong-Ho Lee, Seoul National University

	Memory landscape evolution in the time of A.I. Yangyin Chen, Western Digital	True random number generator (TRNG) for secure communications in the era of IoT Zhigang Ji, Shanghai Jiaotong University

	Application of Machine Learning for the Reduction of Systematic Defects from Design to Wafer Manufacturing James Word, Mentor Graphics	Challenge of High Power LPP-EUV Source with Long Collector Mirror Lifetime for Semiconductor HVM Hakaru Mizoguchi, Exective Vice President and CTO, Gigaphoton

	Etch Proximity Correction Based on Machine Learning Rui Chen, Associate Professor, IMECAS	Full Chip Curvilinear ILT in a Day Leo Pang, Chief Product Officer and VP, D2S

	Line Width and Roughness Measurement of Advanced FinFET Features by Reference Metrology Masami Ikota, Senior Engineer, Hitachi High Tecnologies	VASE innovation for ultrathin film characterization Zhimin Zhu, Sr. Scientist, Brewer Science

	DRAM, NAND, and Emerging Memory Technology Update Jeongdong Choe, Senior Technical Fellow, TechInsights	2-D Device Scaling to Nanosheet, and Technological Challenges Dr. David Xiao, Program Manager of Core CMOS scaling, IMEC

	Boron Doped Carbon Hardmask Removal with Downstream ICP Plasma Process Jeyta Sahay, Mattson, US	Etch Challenges and Solutions in Si Trench Etch for Power Devices Dr. Shenjian Liu, General Manager, AMEC

	Quasi-Atomic Layer Etching Technology for High Uniformity Etching Applications Yiming Zhang, Naura	14nm Fin SADP Patterning Processes and Process Integration Chunyan Yi, Principle Engineer, Shanghai IC R&D Center

	The Law that Guides the Development of Photolithography Technology and the Methodology in the Design of Photolithographic Process Dr. Qiang Wu, Vice Director, Shanghai IC R&D Center

	Fabrication and Performance Trade-offs of Future Interconnect Design and Material Options Dr. Jonathan Reid, Fellow, Lam Research	Enabling CMOS Logic Technology Scaling beyond FinFETs Dr. Bu Huiming, Director, IBM Research

	Evolution of FINFETS and The Role of Thin Films Dr. Rishikesh Krishnan, Senior Technologist, IBM	Design & Technology Co-Optimization in Advanced Node Dr. AbdelKarim Mercha, Technical Director, IMEC

	BEOL Interconnect Challenges and Solutions for Advanced Technology Node Dr. Zhu Huanfeng, Technologist, Lam Research	3D NAND N-O Stacks Process Strategy Dr. Hongbin Zhu, Sr. Director, YMTC

	Dielectric Technologies for Advanced Logic and Memory Products Terrance Lee, Vice President, Applied Materials	Mechanically Stable Ultra-low k dielectric and Air-gap technology Dr. Mansun Chan, Chair Professor, The Hong Kong University of Science and Technology

	Exploring Aggressive BEOL Scaling Using Electrochemical ALD and ALE of Interconnect Materials Prof. Rohan Akolkar, Professor, Case Western Reserve University

	Pattern loading effect optimization of BEOL Cu CMP in 14nm technology node Zhang Lei, Principal Engineer, HLMC	STOP ON NITRIDE SLURRY DEVELOPMENT Dr. Shoutian Li, Senior Manager, Anji Microelectronics

	Solving CMP challenges for chemically stable materials and 3D shapes Dr. Hitoshi Morinaga, Senior General Manager, FUJIMI Incorporated	Modeling of chemical mechanical polishing incorporating the effect of micro contact of polishing pad Dr. Ping Zhou, Associate Professor, Dalian University of Technology

	Sidewall characterization and 3D-AFM applications Prof. Tae-gon Kim, Hanyang University	The adsorption and removal of corrosion inhibitors during metal CMP Prof. Jin-Goo Park, Hanyang University

	Lead the Future Dr. Manabu Tsujimura, Fellow, Ebara Corporation

	High-Level Approaches to Hardware Security Prof. Ramesh Karri, Professor, New York University	Machine and Deep Learning in optical metrology for Process control Dr. Barak Bringoltz, Director of Modeling Technology, Nova measuring instruments

	Transition Induced Internal CDM-ESD liked Damage inside the IC Dr. Tung-Yang Chen, President, AIP Technology

	3D Heterogeneous Advanced Packaging and Manufacturing Dein Wang, Director, TSMC	Semiconductor Heterogenous Integration and Supper Intelligence in the Post Moore's Law Era Dr. Hu Chuan, Chief Expert, Guangdong Academy of Sciences

	Integrated Photonics for Life Sciences - Cytometry and Microscopy Dr. Qingzhong Deng, IMEC	3D Heterogeneous Integration Dr. Bill Bottoms, Chairman and CEO, 3MTS

	Evolution of Smart Sensors and AI at the Edge Keith Nicholson, Director, Bosch Sensortec GmbH	Monolithic integration of optical MEMS on CMOS Christoph Hohle, Fraunhofer IPMS

	Minimum Energy Operation of Voltage-Scaled Circuits Prof. Hidetoshi Onodera, Professor, Kyoto University	Monolithic 3D enabled Processing-in- SRAM Memory Prof. Vijaykrishnan Narayanan, Distinguished Professor, Pennsylvania State University

	A Classification Framework Using Incorrectly Labeled Data for Manufacturing Applications Prof. Xin Li, Professor, Duke University	Optical Networks-on-Chip (ONoCs): EDA Achievements Prof. Ulf Schlichtmann, Professor, Technical University of Munich

	DREAMPlace 2.0: an Open-Source GPU-Accelerated Global and Detailed Placement for Large-Scale VLSI Designs Prof. Yibo Lin, Assistant Professor, Peking University	Greedy Dynamic Power (GDP): Power Budgeting and Thermal Management of Multi-Core Systems in the Dark Silicon Era Prof. Hai Wang, Associate Professor, the University of Electronic Science and Technology of China

	Energy-Efficient Inverter-Based Amplifiers: From fundamentals to the state-of-the-arts Prof. Youngcheol Chae, Associate Professor, Yonsei University	A Clock Jitter Tolerant Σ∆ Modulator Employing A Hybrid Loop Filter In CMOS 40nm Technology Prof. Jose Silva-Martinez, IEEE Fellow, Texas A&M University

	Learning-Based Power Modeling and Optimization for FPGA Prof. Wei Zhang, Associate Professor, the Hong Kong Univesity of Science and Technology	Reliable Design for 3D ICs: From Microarchitecture and Physical Design Perspectives Prof. Yuanqing Cheng, Assistant Professor, Beihang University

Confirmed Distinguished Workforce Development Speakers

	Advanced Memory Technologies: MRAM Dr. Shu-Jen Han, Senior Director, HFC Semiconductor Corp.	Advanced Memory Technologies: ePCM/3D-PCM Dr. Yu Zhu Executive Assistant to CEO, Jiangsu Advanced Memory Semiconductor (AMS) Co., Ltd

	Semiconductor Testing Solutions in the Trend of 5G and AI Liang Ge R&D manager and Test strategy leader, Advantest China	Heterogeneous Integration and Advanced Packaging Dr. Bill Bottoms, Chairman and CEO, 3MTS

	IC Reliability Tests for 5G Applications Xu Feng, Deputy General Manager & Technology Director, JCET quality test center